use Verilog::VCD::Writer; my $writer=Verilog::VCD::Writer->new(vcdfile=>'test.vcd'); my $m1=$writer->addModule("Utop"); #Create top level module Utop my $m2=$writer->addModule("UDUT"); #Add Submodule UDUT my $TX=$m1->addSignal("TX"); #Add TX signal to toplevel my $RX=$m1->addSignal("RX",3,0); # Add a vector RX signal my $s3=$m1->addSignal("c",3,1); my $s4=$m2->dupSignal($RX,"b",0,3); #Duplicate RX from top inside DUT my $s5=$m2->dupSignal($TX,"a"); #ditto for TX my $s6=$m2->addSignal("cat"); $writer->writeHeaders(); # Print the VCD header $writer->setTime(0); #Set Initial time $writer->addValue($TX,0); # Value change on Tx $writer->addValue($RX,0); $writer->addValue($s3,0); $writer->setTime(5); # Increment time to 5 $writer->addValue($TX,1); #TX Value Change $writer->addValue($RX,0); $writer->addValue($s6,0); ....
VCD(Value Change Dump) is the default way of recording waveform information for a HDL(Verilog/VHDL/SystemC/SystemVerilog) simulation.
This module provides an implementation of a VCD Writer.
The module originally started as a quick and dirty perl script to convert the CSV file generated by a logic analyzer into a VCD file.
For the release on CPAN the original code has been heavily modified and cleanedup so as to meet other waveform generation needs.