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Verilog::VCD::Writer creates VCD waveform files

VCD(Value Change Dump) is the default way of recording waveform information for a HDL(Verilog/VHDL/SystemC/SystemVerilog) simulation.

This module provides an implementation of a VCD Writer.

The module originally started as a quick and dirty perl script to convert the CSV file generated by a logic analyzer into a VCD file.

For the release on CPAN the original code has been heavily modified and cleanedup so as to meet other waveform generation needs.

jahagirdar@github 3 comments