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SVG::Timeline::Compact Compact SVG Timeline Drawing Module

This module originated because SVG::Timeline did not meet my requirements.

I communicated with the author and went through the code with an intention of contributing to it, but realized that it follows a different design philosophy and use case.

The major difference with SVG::Timeline are as follows

  • Start and End are actual DateTime Objects.
  • Auto-calculation of timescale ( min, hours, days, months, years ) based on the events and grid size.
  • Auto Layout to fit multiple events on same row.
  • Tooltips.

jahagirdar@github 0 comments

Verilog::VCD::Writer creates VCD waveform files

VCD(Value Change Dump) is the default way of recording waveform information for a HDL(Verilog/VHDL/SystemC/SystemVerilog) simulation.

This module provides an implementation of a VCD Writer.

The module originally started as a quick and dirty perl script to convert the CSV file generated by a logic analyzer into a VCD file.

For the release on CPAN the original code has been heavily modified and cleanedup so as to meet other waveform generation needs.

jahagirdar@github 3 comments